1. Field of the Invention
The present invention relates to wafer level semiconductor testing, and in particular relates to a test board for wafer level semiconductor testing.
2. Description of the Related Art
Packaging is an essential step in the fabrication of integrated circuits, which protects the integrated circuits and provides a signal transmission interface for external circuits. Therefore, the development of packaging is related to the development of integrated circuit technology and the function of electronic products. A variety of packaging technologies have been developed, such as ball grid array (BGA), chip scale package (CSP), flip chip, and multi-chip module (MCM).
A BGA (ball grid array) type semiconductor device using a TAB tape as an interposer is shown as a representative example of these semiconductor devices in FIGS. 1 and 2. This device is a BGA type semiconductor device of the so-called “PSR via type” wherein, while leaving via holes 12 for solder balls (PSR via), an insulating film 2 composed of a photosolder resist (PSR) is provided on a tape substrate 5, composed of an insulating film, on its side where a wiring pattern 3 is provided.
Specifically, FIGS. 1 and 2 show the construction of a conventional semiconductor device. A TAB tape 1 used in the semiconductor device comprises: a tape substrate 5 formed of a polyimide resin insulating film; a wiring pattern 3 which has been formed by bonding a copper foil onto one side of the tape substrate 5 through an adhesive 4 and photoetching the copper foil and has, on its one end, a bonding pad 10 for connection to a semiconductor and has, on its other end or in a portion between both ends thereof, a solder ball mounting pad 30; and an insulating film 2 in a predetermined PSR pattern, which has been formed on the surface of the wiring pattern 3 in the region of the solder ball mounting pad 30 while leaving a via hole 12 for a solder ball, by printing a photosolder resist resin by means of a printing plate on the wiring pattern 3 and subjecting the print to pattern exposure and development. With the TAB tape 1 as a wiring tape for mounting a semiconductor element for wire bonding purposes, a window hole is generally formed in the center portion by stamping, and the insulating film 2 is not formed in the portion of the bonding pad 10 on the tape substrate 5 and a region extended inward from the bonding pad 10. In manufacturing the semiconductor device, shown in FIG. 1, by using this TAB tape 1, a remote side from the wiring pattern 3 (opposite side of the tape substrate 5) of a semiconductor chip 7, is applied through an adhesive 6 onto the tape substrate 5, and an electrode 8 in the semiconductor chip 7 is electrically connected to the bonding pad 10 in the TAB tape through a bonding wire 9 formed of gold. Next, the connection in the wire bonding, that is, the bonding lead portion, is sealed by a mold resin 11. Thereafter, solder balls 13 formed by reflow treatment are mounted respectively on the solder ball mounting pads 30 in such a manner that the solder balls 13 are arrayed in via holes 12 for solder balls.
According to the semiconductor device described, a wiring pattern 3 is provided on the tape substrate on the side opposite to the side on which the semiconductor chip 7 on the element formation surface is put. This construction permits the element electrode 8 in the semiconductor chip 7 to be bonded to the wiring pattern 3 through the bonding wire 9 which is passed through the window hole 15. Therefore, the bonding wire 9 can be provided without being extended around the periphery of the semiconductor chip 7. This can eliminate the need to ensure, on the periphery of the semiconductor chip 7, a wiring space for the bonding wire 9 and thus can reduce the size and thickness of the whole device. Further, since wire bonding can be carried out, a difference in coefficient of thermal expansion between the semiconductor element and the substrate can be absorbed by the bonding wire 9. This is advantageous, for example, in that an inexpensive resin substrate rather than an expensive ceramic substrate can be used. However, it has been found that, in sealing the bonding lead portion by the mold resin, the mold resin spreads on the PSR pattern and flows into the via hole (PSR via) for a solder ball and, consequently, the solder ball disadvantageously detaches from the via hole. While BGA technology offers advantages of higher connection densities on the circuit board and higher manufacturing yields which lowers product cost, it is not without disadvantages. For instance, solder joints cannot be easily inspected, and circuit board level cannot be easily reworked, i.e. correcting problems after attachment of the BGA package to the circuit board, is more difficult since, having no replaceable components, the BGA connectors are typically unserviceable.
Flip chip is also a commonly used packaging method, which employs a solder bump formed on a bonding pad for connection to the circuit board. The formation of the solder bump comprises solder ball mounting, printing, and electroplating. FIGS. 3A to 3D illustrate a conventional method for forming a solder bump structure by electroplating.
As shown in FIG. 3A, a substrate 100, such as a silicon substrate, is provided. The substrate 100 has a metal bonding pad 102 comprising, for example, aluminum or copper. A passivation layer 104, such as a silicon nitride layer, is formed overlying the substrate 100 and substantially exposes the metal bonding pad 102. A metal composite layer 106 is conformably formed on the passivation layer 104 and the exposed metal bonding pad 102, which is typically a metal stack of adhesion layer/barrier layer/wetting layer. In order to simplify the diagram, a single layer is depicted. As shown in FIG. 3B, a dry pattern film 108 is formed on the metal composite layer 106, which has an opening 109 to expose a portion of the metal composite layer 106 overlying the metal bonding pad 102. Here, the opening region 109 is utilized in forming solder bump. Accordingly, the opening 109 is subsequently filled with a solder 110 by electroplating. The height of the solder is determined by the thickness of the dry pattern film 108. As shown in FIG. 3C, the dry pattern film 108 is removed and the metal composite layer 106 is uncovered by the solder 110 and then removed, exposing the underlying passivation layer 104. The remaining metal composite layer 106a acts as an under bump metallurgy (UBM) layer. As shown in FIG. 3D, a reflow process is performed, such that the solder 110 forms a ball-shaped or hemiball-shaped solder bump 110a due to surface tension.
The height of the solder bump, however, affects reliability of packaging devices. As the size of the package is reduced, fatigue strength is degraded if the height of the solder bump is too low, reducing the bonding life. Moreover, during bonding of the chip to the circuit board, the gap between the chip and the circuit board cannot be effectively filled with the underfill, thus forming holes therein. Accordingly, the reliability of the flip chip method can be increased by providing higher solder bump. Generally, the methods for increasing the height of the solder bump are to increase the dry film thickness or size of the UBM layer, thereby increasing the capacity of the solder to accomplish the higher solder bump. Unfortunately, such methods may be detrimental for lithography or increase the occupied area of the chip, reducing the integration. Similarly to BGA technology, for flip chip technology, solder joints cannot be easily inspected, and circuit board level cannot be easily reworked, i.e. correcting problems after attachment of the solder bump package to the circuit board, is more difficult since, having no replaceable components, the solder bump connectors are typically unserviceable.
Alternatively, in order to achieve compactness, semiconductor devices having a semiconductor package in the size of a chip referred to as CSP have also been developed. The size of CSP is substantially the same as that of the chip or slightly larger than the chip. There is the resin sealed type semiconductor device which is referred to as a Wafer Level Chip Scale Package/Wafer Level Chip Scale Package (hereinafter W-CSP) among CSP. The size of W-CSP is the same as that of the chip. The conventional CSP type semiconductor device will be described with reference to FIG. 4. FIG. 4(a) is a plane view showing the conventional semiconductor device having a wafer level chip size package structure individually divided from a wafer. FIG. 4(b) is a cross sectional view taken along line DD′ of the conventional semiconductor device shown in FIG. 4(a).
The conventional semiconductor device comprises a semiconductor chip 1000, an oxide film 1001, a plurality of electrical pads 1002, an insulating film 1003, a plurality of redistributions 1004, a plurality of posts 1005, a plurality of solder bumps 1006 and a sealing resin 1007. The semiconductor chip 1000 has a main surface having a central area 1000a and a peripheral area 1000b surrounding the central area 1000a. A circuit, e.g. a transistor etc, is formed on the main surface in the peripheral area 1000b. There is nothing on the main surface in the central area 1000a. The oxide film 1001 is formed on the main surface of the semiconductor chip 1000 in all areas. The electrical pads 1002 are formed on the oxide film 1001 in the peripheral area 1000b. The electrical pads 1002 are electrically connected to the circuit formed on the semiconductor chip 1000. The insulating film 1003 is formed on the oxide film 1001 in all areas and on the electrical pads 1002. The redistributions 1004 are formed on the electrical pads 1002 and the insulating film 1003 in the peripheral area 1000b. The redistributions 1004 are electrically connected to the electrical pad 1002. The posts 1005 are formed on the redistributions 1004 being formed on the insulating film 1003 and are electrically connected to the redistributions 1004. The solder balls 1006 are formed on an end of the posts 1005 and are electrically connected to the posts 1005. The sealing resin 1007 seals the insulating film 1003, the redistributions 1004 and side surfaces of the posts 1005.
For conventional CSP type semiconductor devices, similar packaging inefficiencies mentioned previously, are also seen. That is, solder joints cannot be easily inspected, and circuit board level cannot be easily reworked, i.e. correcting problems after attachment of the package to the circuit board, is more difficult since, having no replaceable components, the connectors are typically unserviceable.